The present invention relates generally to semiconductor devices and more specifically to a method and system for eliminating voids in semiconductor devices.
Semiconductor manufacturers have increasingly turned to high density Metal Oxide Semiconductor (MOS) arrays in their integrated circuit design schemes. To achieve a high density integrated circuit, features such as metal-oxide semiconductor field-effect transistors (MOSFETs) must be as small as possible. This means scaling down metal thickness as spacer gaps are narrowed, thereby increasing the MOSFET aspect ratio. Typically, of these high density flash memory integrated circuits utilize NAND-type gates as opposed to NOR-type gates since NAND gates have a considerably higher density than NOR gates. Smaller transistors allow more transistors to be placed on a single substrate, thereby allowing relatively large circuit systems to be incorporated on a single, relatively small die area.
FIG. 1 illustrates a cross section of metal lines that can form the inner connect to device transistors. The metal lines 100 and 150 are on a substrate surface 108. The metal lines 100, 150 are separated by a spacer gap 104. A dielectric oxide liner 110 is deposited using a conventional chemical vapor deposition (CVD) methodology. A spin-on glass (SOG) 112 is then applied, followed by the application of a topside dielectric film 114.
For a better understanding of a conventional method of processing a semiconductor device please refer to the flowchart of FIG. 2. Once the metal lines are in place, a first oxide liner is deposited using a CVD technique, via step 200. Next, a spin-on glass is utilized to form a second oxide layer, via step 202. Finally, a protective topside dielectric film is formed, via 204.
The deposition of a dielectric film with uniform electronic properties is desirable since unaccounted for changes in the properties of the dielectric layer can produce drastic changes in the performance of the semiconductor device. However, as dimensions are reduced in each new generation of integrated circuit, it becomes more difficult to deposit dielectric material on the top metal layer utilizing conventional methodology. For example, as a result of smaller metal lines and gaps (0.35 microns or lower), the formation of voids during the conventional process becomes a significant concern. Voids create weaknesses in the topside dielectric film which reduces the reliability of the device.
Accordingly, what is needed is a method for eliminating voids in the topside dielectric film of semiconductor devices. The present invention addresses such a need.
The present invention is a method and system for eliminating voids in a semiconductor device. The method comprises the steps of forming metal lines over a semiconductor substrate, forming a first oxide layer utilizing a high density plasma deposition technique, forming a second oxide layer utilizing a carbon free resin and forming a topside dielectric layer.
Through the use of a method in accordance with the present invention, the voids that are created in the dielectric films during conventional semiconductor processing methodology are eliminated. The use of a high density plasma deposition technique provides a more directional deposition that can get between metal lines that are separated by smaller gaps. The dielectric films are thereby strengthened, which increases the reliability of the semiconductor device. Furthermore, by utilizing hydrogen silsesquiloxane instead of a conventional spin-on glass, there is no concern regarding carbon contamination since hydrogen silsesquiloxane doesn""t contain carbon atoms.